Memories frequently are structured in a hierarchical manner whereby each memory array sector bit line is driven by multiple global bit lines. Each global bit line in turn is driven by multiple local bit lines. Bit line driving circuitry therefore is used to permit each bit line at one level to carry a bit value from one of a number of bit lines at a lower level. Conventional bit line driving circuitry typically is dynamic circuitry using clock signaling to avoid contention issues between two or more bit lines for control of a higher-level bit line.
Memories employing a hierarchical bit line structure typically are configured such that the routing and configuration of metal routes proximate to higher-level bit lines (e.g., metal routes in the substrate layers above or below a global bit line) are uncontrolled. As a result, noise emanating from the proximate metal routes can result in spurious operation of a higher-level bit lines due to their dynamic operation and reliance on keeper circuitry. A noise-tolerant technique for contention-free access to a higher-level bit line by two or more lower-level bit lines therefore would be advantageous.
The use of the same reference symbols in different drawings indicates similar or identical items.